Memory fault models, MBIST (Memory BIST) methods, and functional procedures.
It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms. Digital System Test and Testable Design: Using ...
The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage Memory fault models, MBIST (Memory BIST) methods, and
The text treats testing and testability as integral parts of the digital design process rather than afterthoughts. Key Technical Coverage The text treats testing and
A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.
This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .
Logic BIST basics, test pattern generation, and output response analysis.