: The PC places the address on the bus; ALE latches it. The processor fetches 2Bh . In T4cap T sub 4

: 5 (Opcode Fetch, Memory Read, Memory Read, Memory Read, Memory Read) T-States : 2. Breakdown of Machine Cycles The timing diagram is divided into five distinct phases: Machine Cycle Description M1 Opcode Fetch 4 T-states Fetches the opcode 2Bh from memory. M2 Memory Read 3 T-states Reads the lower-byte of the 16-bit address ( M3 Memory Read 3 T-states Reads the higher-byte of the 16-bit address ( M4 Memory Read 3 T-states

: The processor increments the address by 1, reads the next byte, and stores it in the H register .